1. Field of the Invention
The present invention relates generally to semiconductor wafers, and more particularly to an enhanced sampling method for semiconductor wafers.
2. Background of the Invention
Prior to shipment, a sampling of semiconductor wafers is tested for satisfaction of performance requirements of the die on the wafer. In accordance with prior art sampling methods, if the predicted yield of the entire semiconductor wafer does not meet yield requirements, the entire wafer, lot of wafers, e.g. batch, or even shipment of wafers will be labeled as “bad,” discarded, and not shipped. Prior art semiconductor wafer sampling methods are fraught with problems.
Prior art sampling methods waste fabrication resources, which consequently results in delayed or cancelled semiconductor shipments, by incorrectly presuming a random distribution of failures, e.g. bad die, on a semiconductor wafer. Because prior art sampling methods presume a random bad die distribution, if bad die are sampled, the entire semiconductor wafer, or worse yet lot or shipment, is labeled as “bad,” discarded, and not shipped.
Moreover, prior art sampling methods are inefficient, which also results in delayed or discarded semiconductor shipments. Because prior art sampling methods are time consuming, only a small population of semiconductor wafers, such as a single wafer or batch, is tested for predicted yield. One problem associated with such method is that such a small population rarely represents the predicted yield of an entire lot or shipment, which in turn leads to misguided shipment decisions based upon a misrepresented population of wafers.
Therefore, there remains a need in the art for an improved method for sampling semiconductor wafers, which improves the overall yield of the semiconductor processing line from semiconductor fabrication to shipment.
These and other deficiencies in the prior art are overcome through the present invention.